1. Technical Field
The present invention relates to a semiconductor integrated circuit and more particularly to a semiconductor integrated circuit for carrying out a failure diagnosing operation by using a built-in self test circuit of a memory.
2. Description of the Related Art
In a semiconductor integrated circuit including a memory, there has been used a technique for incorporating a built-in self test (which will be hereinafter referred to as a BIST), carrying out the BIST by using the BIST circuit to detect a defective chip, and subsequently performing a failure diagnosis over the defective chip by using the BIST circuit, thereby extracting a candidate for a defective portion of the memory. Examples of the BIST circuit include a comparator type BIST circuit for comparing an expected value which is identical to write data with data read from the memory and deciding the presence of a failure and a compressor type BIST circuit for compressing the data read from the memory in the BIST circuit and deciding the presence of the failure by using a result of the compression (for example, see JP-A-2005-129174 Publication (Page 11, FIG. 4)).
In the BIST circuit described in the JP-A-2005-129174, it is possible to read a status in a memory by repeating an interruption of a BIST operation, a shift-out and a restart of the BIST operation. Based on the result, it is possible to create a bit failure map indicative of a failure bit position in a cell array of the memory, thereby executing a failure analysis.
Irrespective of the presence of the failure, it is necessary to read all internal statuses and to also shift a register of the memory which is not a failure diagnosing target. For this reason, there is a matter in that a time required for the test is prolonged enormously. Moreover, there is a matter in that a size of a test pattern for carrying out a failure diagnosis through the BIST is increased greatly. In addition, there is a matter in that it is hard to acquire failure diagnosis information which is equivalent to a result of an actual speed test.